1. Field of the Invention
The present invention relates to a conductive line of a semiconductor device and a method of fabricating a conductive line, and more particularly, to a conductive line of a semiconductor device having at least two different values of curvature and a method of fabricating the same.
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits (ICs), semiconductor devices are generally connected by several metallic interconnecting layers commonly referred to as multi-level interconnects. When the integration of semiconductor devices in the semiconductor integrated circuits increases, improving the process of forming the structure of multi-level interconnects gets more important. The multi-level interconnects usually include dielectric layers and metal layers disposed alternately. The process of manufacturing multi-level interconnects includes the following steps. A patterned conductive layer is formed on a substrate, followed by forming a dielectric layer covering the conductive layer. Subsequently, a plurality of contact plugs electrically connected to the conductive layer is formed in the dielectric layer. Then, another conductive layer electrically connected to the contact plugs is formed on the dielectric layer. After the formation of the conductive and dielectric layers, a passivation layer is finally selectively disposed thereon to complete the formation of the multi-level interconnects.
The dielectric layer and the passivation layer mainly provide insulation and protection functions. For different purposes, some parameters of the dielectric layer and the passivation layer, such as the electric constant, the material strength, and the stress between the materials and other materials in contact with the dielectric layer or the passivation layer, must be considered. Generally, the dielectric layer and the passivation layer are made of silicon oxide or silicon nitride. Since silicon nitride is more rigid, it is therefore mostly selected as a passivation layer in semiconductor devices. The semiconductor processes are various for achieving different requirements; if the thickness of the conductive layer is too large, or the integration of the conductive layer is too high, the dielectric layer or the passivation layer covering the conductive layer may be affected, and the step coverage effect of the dielectric layer or the passivation layer may therefore be deteriorated, overhang may form when the dielectric layer or the passivation layer is used to fill in the space between two conductive layers, cracks in the dielectric layer or the passivation layer may be induced at the corner of the conductive layer due to high stress between the dielectric layer or the passivation layer and the conductive layer.
Consequently, how to prevent the formation of cracks in the dielectric layer or the passivation layer due to the excessive thickness of the conductive layer, so as to improve the performances of the semiconductor device is still an important issue in the field.